1. Field of the Invention
The present invention relates to a semiconductor memory including a plurality of memory devices and one control circuit which are connected through signal bus lines and a data bus lines. More specifically, the present invention relates a semiconductor memory including a plurality of memory devices, called a synchronous DRAM, having a high data transfer rate.
2. Description of Related Art
Recently, the semiconductor memory is constituted as a synchronous DRAM. This synchronous DRAM is so configured that a reading and a writing are executed in synchronism with a clock signal supplied from an external. Therefore, since a command signal and a reading address can be inputted in advance, a continuous data can be read out at a high speed.
A general synchronous DRAM system includes a plurality of synchronous DRAMs (M#1 to M#n) parallel-connected to a memory controller (MC), so that an operation of the memory is controlled by control signals. The control signals include a clock signal CLK, a RAS (row address strobe) signal RASB, a CAS (column address strobe) signal (CASB), a write enable signal (WEB). Here, the RAS signal, the CAS signal and the write enable signal are called "command signals", and various commands are formed by combinations of a high level (1) and a low level (0) of respective signals.
The commands includes a read command for reading data from the synchronous DRAMs M#1 to M#n, and a write command for writing data into the synchronous DRAMs M#1 to M#n. The read command is designated with a combination of RASB=1, CASB=0 and WEB=1, and the write command is designated with a combination of RASB=1, CASB=0 and WEB=0. In addition, these commands are timing-controlled by the clock signal CLK, and the conditions of the RAS signal RASB, the CAS signal CASB and the write enable signal WEB are recognized at the time the clock signal CLK changes from "0" to "1".
As well known, the clock signal CLK is a signal of cyclically and alternately repeating "0" and "1". In order to determine the command at what time should be executed by the synchronous DRAM, and in order to specify which of the synchronous DRAMs M#1 to M#n is given with the command, chip select signals CS#1 to CS#n are supplied to the synchronous DRAMs M#1 to M#n, respectively. The chip select signal supplied to only the synchronous DRAM to which the command should be given, is brought to "1" at the timing the command should be applied. Furthermore, an address bus (ADD.BUS) for designating an address of a memory cell in each synchronous DRAM and a data bus (DATA.BUS) for transferring data between the memory controller and the synchronous DRAMs M#1 to M#n.
Referring to FIG. 8, there is shown a block diagram for illustrating a signal connection between the memory controller and the synchronous DRAMs in the prior art, but for simplification of the drawing, only one synchronous DRAM M#i representative of the synchronous DRAMs M#1 to M#n is shown, and the chip selection signal is omitted.
The clock signal CLK, the command signals RASB, CASB and WEB and the address bus ADD.BUS are unidirectional signals from the memory controller MC to the synchronous DRAM M#i, and therefore, the memory controller MC includes drivers for respective signals (CLOCK DRIVER 1, COMMAND DRIVER 1, COMMAND DRIVER 2, COMMAND DRIVER 3, ADDRESS DRIVER 1 to ADDRESS DRIVER M), and the synchronous DRAM M#i includes receivers for receiving the respective signals (CLOCK RECEIVER 1, COMMAND RECEIVER 1, COMMAND RECEIVER 2, COMMAND RECEIVER 3, ADDRESS RECEIVER 1 to ADDRESS RECEIVER M). However, since the data bus transfers a bidirectional signal between the memory controller MC and the synchronous DRAM M#i, each of the memory controller MC and the synchronous DRAM M#i includes drivers and receivers (DATA DRIVER 1 to DATA DRIVER n and DATA DRIVER 1 to DATA DRIVER n).
The clock receiver generates an internal clock ICLK, which is used for latching the command, the address and the data and for outputting the data. For this purpose, the receivers are respectively connected to latches controlled by the internal clock ICLK (COMMAND LATCH 1, COMMAND LATCH 2, COMMAND LATCH 3, ADDRESS LATCH 1 to ADDRESS LATCH m, DATA LATCH 1 to DATA LATCH n), and the drivers are connected to data output circuits controlled by the internal clock ICLK (DATA OUTPUT CIRCUIT 1 to DATA OUTPUT CIRCUIT n). Here, the latch latches the signal at the time the clock signal changes from "0" to "1" and holds the same signal until a next cycle, namely, at the next time the clock signal changes from "0" to "1".
With this arrangement, after the clock signal has changed from "0" to "1", even if for example the RAS signal RASB is caused to change from "1" to "0", this change of the RAS signal RASB is not transferred to the COMMAND LATCH 1 internally provided in the synchronous DRAM M#i and its downstream side circuits. This operation can be rephrased as the command is acknowledged at each clock cycle.
Here, the write/read operation will be described with reference to FIGS. 9 and 10. FIG. 9 is a timing chart of the signals supplied to different synchronous DRAMs M#i for illustrating the write operation. "#+number" added at the end of signal names corresponds to the DRAM number.
First, the clock #0 cyclically repeats "0" and "1", The command #0 corresponds to a blanked portion, and is latched at the time the clock #0 changes "0" to "1" in the synchronous DRAM M#0. Cross-hatched portions in the command #0 and in the address #0 corresponds to a period in which the chip select signal CS#0 is "0", and the blanked portion corresponds to the period in which the chip select signal CS#0 is "1".
In the case that the chip select signal CS#0 is "0", the signals constituting the command are not received by the synchronous DRAM M#i regardless of the level (1 or 0) of each of the signals constituting the command. This is true in the address #0. The data #0 assumes, in addition to "0" and "1", a "Hi-z" condition taking an intermediate potential between the potential of "0" and the potential of "1", which corresponds to the condition in which no data to be written exists on the data bus in the write operation period and the condition in which no read-out data exists on the data bus in the read operation. The data to be written is given at the same time as the write command and the column address are given to the synchronous DRAM M#0.
A similar write operation is carried out in each of the synchronous DRAMs M#2 and M#4. In FIG. 9, Td#2 and Td#4 are a delay time required until the clock, the command signals and the address reach from the memory controller MC to the synchronous DRAMs M#2 and M#4, respectively. The delay time is considered by using the synchronous DRAMs M#0 as the reference, since the synchronous DRAMs M#2 is located physically nearest to the memory controller MC and therefore, since the delay time from the memory controller MC to the synchronous DRAMs M#0 can be considered to be substantially "0" (zero).
A cause of the delay time is a parasite resistance and a parasite capacitance of each signal line, and is substantially in proportion to the wiring distance. Accordingly, the delay time Td#4 is larger than the delay time Td#2. In particular, since the data bus has the parasite capacitance larger than that of the command signals, the address signals and the clock signal, the delay time Tdd#2 of the data is larger than the delay time Td#2 of the other signals, and similarly, the delay time Tdd#4 of the data is larger than the delay time Td#4 of the other signals. The following is the reason for why the parasite capacitance of the data bus is large: As seen from FIG. 8, each synchronous DRAM M#i includes both the receiver and the driver for only the data bus, and a number of synchronous DRAMs M#i are provided, with the result that the parasite capacitance becomes large by the parasite capacitance of the drivers.
In FIG. 9, the time defined as "Ts#i" is called a setup time. The setup time of the data bus in the synchronous DRAMs M#2 and M#4 are expressed as Tsd#2 and Tsd#4, respectively. As seen from FIG. 9, the setup time is defined by using the clock as the reference, and therefore, the clock signal, the command signals and the address signals have the same delay time. Therefore, the setup time of these signals has no location dependency. However, the delay time of the data is larger than that of the other signals, the setup time of the data to be written becomes short with increase of the wiring distance from the memory controller.
Next, the read operation will be described with reference to FIG. 10. In the read operation, the read command and the address are given similarly to the write operation. Td#2 and Td#4 indicate a delay time. The read operation is different from the write data in that the time where the data to be read is actually read out, is different from the time where the command and the address are given from the memory controller MC. In the synchronous DRAMs M#i, the times Tac#0, Tac#2, and Tac#4 are required respectively after each synchronous DRAM receives the read command and the address from the memory controller MC before the data is actually read out onto the data bus. These times are equal to one another. Therefore, for example, the data to be read in the synchronous DRAMs M#2 is read out with a delay of Td#2+Tac#2 from the clock #mc in the memory controller MC.
This delay time becomes Td#2+Tac#2 in the synchronous DRAMs M#4. Furthermore, times Tddf#2 and Tddf#4 are required, respectively, until the read-out data reaches the memory controller MC. The read-out data having reached the memory controller MC is designated with data #mcf2 and data #mcf4, respectively, in FIG. 10. Here, the setup time of the read-out data is defined in comparison with the clock #mc of the memory controller MC receiving the read-out data, differently from the setup time of the write operation which is defined in comparison with the clock #i in the respective synchronous DRAM M#i. In the example shown in FIG. 10, the setup time of the data #mcf0 corresponds to Tsdf#0, and the setup time of the data #mcf2 corresponds to Tsdf#2. However, since the delay time of the data #mcf4 is too large, the data #mcf0 becomes later than the reference timing point, with the result that no setup time can be obtained.
Here, the role of the setup time in the synchronous DRAM will be described with reference to FIGS. 11 to 13. FIG. 11 is a circuit diagram of a latch circuit of latching an input signal IN through a transfer gate TG as an output signal OUT. FIGS. 12 and 13 are timing charts of a latch signal .phi., the input signal IN and the output signal OUT for illustrating an operation of the latch circuit shown in FIG. 11. FIG. 12 illustrates a problem in the case that a sufficient setup time cannot be obtained, and FIG. 13 illustrates a problem in the case that a sufficient hold time cannot be obtained. Here, the hold time is defined to be a length of time in which the input signal IN is held after the latch signal .phi. is brought from "0" to "1" (namely, after the inverted latch signal .phi.B is brought from "1" to "0"), and indicated by Thold in FIG. 13. The setup time is shown by Tsetup in FIG. 12.
The example shown in FIGS. 11 to 13 illustrate a situation that "1" is applied to the input IN, and is held at the output OUT when the latch signal .phi. is brought to "1". Here, assuming that the Tsetup is too short, the transfer gate TG is closed before the output OUT is sufficiently changed, with the result that the output OUT is not completely fixed to "1" and is returned to "0". This is the problem in the case that the setup time is too short. To the contrary, if Thold is too short, the output is changed to the level of "1" and becomes stable at the level of "1" once, however, in the course of the closing operation of the transfer gate TG, the input IN is changed from "1" to "0", with the result that the output OUT is returned to the level of "0". This is the problem in the case that the hold time is too short.
From the above short explanation, it would be understood that if both the setup time Tsetup and the hold time Thold of a necessary and sufficient value are not ensured, the signal can be properly transferred between the memory controller and the synchronous DRAMs M#i.
Recently, however, the frequency of the clock signal has increased, and therefore, the clock period correspondingly has become short, so that the maximum time of the total value of the setup time and the hold time has become substantially equal to the clock period, or equal to the clock period (not larger than 5 ns) attributable to the delay time (1 ns to 2 ns) of the signal interconnection, with the result that a sufficient setup time cannot be ensured. In addition, The problem that a sufficient hold time cannot be obtained, has been discussed actively. Because of this problem, it is not possible to elevate the clock frequency or the operation speed in a system for transferring a large amount of data for a short time. The reason for this is clearly illustrated in FIG. 10.
In the example shown in FIG. 10, the data #mcf4 read out from the synchronous DRAMs M#4 becomes out of time from the latching time of the memory controller MC, and a necessary and sufficient setup time Tsdf#2 for the data #mcf2 read out from the synchronous DRAMs M#2 cannot be obtained. In the write operation shown in FIG. 9, the setup time Tsd#4 becomes short, but is not so remarkable in comparison with the read operation shown in FIG. 10. The reason for this is as follows: In the write operation, all the command, the address and the data to be written are transmitted in the same direction from the memory controller MC to the synchronous DRAM M#i, but in the read operation, the transmission direction of the command and the address is opposite to the transmission direction of the read-out data, with the result that the delay time becomes larger than that in the write operation, dependently upon the location of the synchronous DRAM. Accordingly, it is important to improve the setup time in the read operation.
Here, assume that in order to improve the setup time in the read operation, the synchronous DRAM M#i is so modified to shorten the reading delay time Tsc#i and to elongate Tsdf#i in FIG. 10. In this case, to the contrary, the hold time of the data read out from the synchronous DRAM M#i located near to the memory controller MC, for example, the hold time Thdf#0 of the data #mcf0, becomes too short, so that the above mentioned problem occurs. Namely, if the data reading-out time is shifted in advance similarly in all the synchronous DRAMs M#i, the setup time Tsdf#2 of the data #mcf2 from the synchronous DRAM M#2 located at a remote side from the memory controller, is improved. However, if the data reading-out time was shifted in advance to cause the data #mcf4 to have a sufficient setup time, the hold time Thdf#0 of the data #mcf0 cannot be obtained. Under this circumstance, it is considered that it is the best way to make the delay time of the signal interconnection as small as possible.
A specific example of this method will be now described as a second prior art. This second prior art method is disclosed in Japanese Patent Application Pre-examination Publication No. JP-A-03-222192 and U.S. Pat. No. 5,384,739 claiming the Convention Priorities based on seven Japanese patent applications including the application of JP-A-03-222192, (the content of U.S. Pat. No. 5,384,739 is incorporated by reference in its entirety into this application). This prior art example is so configured that, in a memory with a logic function, having a plurality of random access memories, a clock signal of an ECL level are supplied and distributed to each random access memory while maintaining the ECL level, and a clock distributing circuit in common to the respective random access memories is located at a center portion of a semiconductor substrate surface so as to minimize the variation in the distance from the respective random access memories to the clock distributing circuit. In addition, each random access memory is provided individually with a clock switch amplifier for generating an internal clock signal of a MOS level on the basis of a predetermined clock signal, and a write pulse generating circuit for generating, on the basis of the internal clock signal, a predetermined write enable pulse which is required for a write operation and which has an adjustable rising timing and an adjustable signal amplitude. With this arrangement, a skew between the internal clock signal and the write enable pulse and skew in the write enable pulse between the respective random access memories are minimized, so that the write operation of the memory with the logic function can be speeded up.
The above mentioned second prior art can achieve some degree of improvement. However, the second prior art is not satisfactory in the present advanced technology which has rapidly shortened the clock period, with the delay time attributable to the wiring becomes remarkable anew. Therefore, it is strongly desired to essentially overcome the above mentioned problems.